1. Field of the Invention
This invention relates to a MIS transistor and a manufacturing method thereof, and more specifically, to a salicide process using a refractory-metal silicide film.
2. Description of the Background Art
The following description is about a general and conventional self-aligned silicide process for forming a refractory-metal silicide film, with reference to FIGS. 10 to 13. A well 1a, an isolation oxide film 2 and an impurity layer 3 for controlling a threshold voltage are formed in a silicon substrate 1. Then, an oxide film, for example, with 6.5 nm thickness is formed on the silicon substrate 1, and 200 nm polycrystalline silicon to be a gate electrode is deposited on the oxide film. After given patterning by a photolithography process, the polycrystalline silicon is anisotropically etched to form a gate electrode 5. Next formed are lightly doped drain (LDD) regions 6, called xe2x80x9cextensionxe2x80x9d as well, on which the oxide film is deposited by means of chemical vapor deposition (CVD). This oxide film is etched back by reactive ion etching to form sidewall spacer oxide films 7. Further, ion implantation of high concentration provides source/drain regions 8 of high density, and then thermal treatment are performed for activation. FIG. 10 is a sectional view showing the state after the activation.
Next, a salicide process is performed. First, the surface of the silicon substrate 1 is cleaned with an appropriate preliminary treatment to deposit a metal film 9 on a wafer surface (See FIG. 11). The metal film 9 is next heated under an appropriate atmosphere to form silicide films 10 with the polycrystalline silicon of the silicon substrate 1 and the gate electrode 5 (See FIG. 12). The composition of the silicide films 10 is expressed as MSix, where M represents a metal element consisting of the metal film 9 and x is a ratio of number of silicon atoms to the metal atoms. Actually, a rapid thermal annealing with a lamp annealing furnace is often performed in such a case. The rapid thermal annealing with the lamp annealing furnace performed soon after the deposition of the metal film 9 is hereinafter referred to as a first RTA. At this time, silicide reaction does not occur in the upper portions of the isolation oxide film 2 and the sidewall spacer oxide films 7 where no silicon exists, at least leaving the metal film 9 with no reaction on those portions (See FIG. 12). Then, the metal film 9 including the metal M with no reaction is selectively removed while the silicide films 10 consisting of the reacted silicide Msix remains (See FIG. 13). That is basically the end of the salicide process.
When the metal film 9 is made of, for example, cobalt, however, lateral growth is likely to occur in forming a cobalt silicide film  less than CoSi2 greater than  in the first RTA at a thermal annealing temperature of more than 600xc2x0 C. Thus, application of another RTA at a temperature of less than 600xc2x0 C. is required after removing the metal film 9 in the first RTA. In this case, in the process of making CoSi2 of Co and Si, Co2Si is first made, then CoSi, and finally CoSi2.
Very possibly, penetration of the cobalt silicide film under the sidewall spacer oxide films 7 is caused by a diffusion species. In the process of making Co2Si of Co and Si, Co becomes the diffusion species, while Si the diffusion species in the process of making CoSi of Co2Si. The application of the first RTA provides CoSi after making Co2Si of Co and Si. Further, the application of another RTA to the CoSi makes Co a diffusion species in the process of making CoSi2. In the process of making Co2Si and CoSi2, cobalt of a diffusion species is likely to be diffused in the silicon substrate 1, and lateral growth of the cobalt silicide film under the sidewall spacer oxide films 7 becomes remarkable. A rapid thermal annealing with a lamp annealing furnace is often performed in this case as well. Such thermal annealing with the lamp annealing furnace performed after removing the metal film 9 with no reaction is hereinafter referred to as a second RTA. Further, when the diffusion species in the formation of the silicide films is silicon such as TiSi2, such penetration does not occur.
With the above-described process, an electrode can be selectively formed in a region exposing a silicon surface, which is the advantage of the salicide process. Further, when gate length is shorter, increase in a gate resistance in cobalt silicide is more moderate than that in titanium suicide. Thus, a high-density integrated circuit with a MIS transistor can be easily achieved through the use of cobalt silicide in the manufacturing process of the MIS transistor.
A MIS transistor produced by a conventional salicide process has recently improved in high density, and its gate length has become shorter and shorter, making a sidewall spacer smaller and smaller in width. With the application of the salicide process using cobalt as a metal M producing silicide reaction, penetration of the silicide films 10 formed on the source/drain regions occurs under the sidewall spacer oxide films 7 formed of the oxide film with the length L1 as shown in FIG. 13. This penetration of the silicide films causes deterioration in a gate breakdown voltage, decrease in reliability of a gate oxide film, and an electrical short between a gate and source/drain electrodes, which is especially serious in a gate electrode with small geometries.
The present invention is directed to a MIS transistor. According to a first aspect of the present invention, the MIS transistor comprises a silicon substrate; a gate insulation film formed on the silicon substrate; a gate electrode formed on the gate insulation film; a sidewall spacer including a silicon nitride layer, formed on both sides of the gate electrodes on the silicon substrate in contact with the silicon substrate; and a silicide film formed outside of the sidewall spacer in the silicon substrate, the silicide film including a metal to be diffusion species for silicon in silicide reaction.
Preferably, according to a second aspect of the present invention, in the MIS transistor of the first aspect, the sidewall spacer includes: a buffer layer formed on both sides of the gate electrodes on the silicon substrate in contact with the silicon substrate; and a silicon nitride layer formed on the buffer layer.
Preferably, according to a third aspect of the present invention, in the MIS transistor of the second aspect, the buffer layer in the sidewall spacer consists of nitrided oxide silicon.
The present invention is also directed to a manufacturing method of a MIS transistor. According to a fourth aspect of the present invention, the manufacturing method of a MIS transistor comprises steps of: forming a gate insulation film and a gate electrode, both of a MIS transistor, on a silicon substrate; forming a sidewall spacer including a silicon nitride layer, on both sides of the gate electrodes on the silicon substrate in contact with the silicon substrate; and a forming silicide film outside of the sidewall spacer in the silicon substrate by using a metal to be a diffusion species for silicon on a silicide reaction.
Preferably, according to a fifth aspect of the present invention, in the manufacturing method of a MIS transistor of the first aspect, the step of forming a sidewall spacer further includes steps of: forming a buffer layer on both sides of the gate electrodes on the silicon substrate in contact with the silicon substrate; and forming the silicon nitride layer on the buffer layer.
Preferably, according to a sixth aspect of the present invention, in the manufacturing method of a MIS transistor of the second aspect, the buffer layer in the sidewall spacer consists of nitrided oxide silicon.
In the MIS transistor of the first aspect of the present invention, suppression of lateral diffusion of the metal, a diffusion species in forming silicide, by the silicon nitride layer in the sidewall spacer prevents deterioration in gate resistance, decrease in reliability of a gate oxide film, and electrical short between a gate and source/drain electrodes.
In the MIS transistor of the second aspect of the present invention, suppression of the production of an interface state by the buffer layer in the sidewall spacer prevents deterioration in transistor characteristics.
In the MIS transistor of the third aspect of the present invention, the MIS transistor has improved in hot carrier resistance.
In the manufacturing method of the MIS transistor of the fourth aspect of the present invention, suppression of lateral diffusion of the metal, a diffusion species in forming silicide, by the silicon nitride layer in the sidewall spacer prevents deterioration in gate resistance, decrease in reliability of a gate oxide film, and electrical short between a gate and source/drain electrodes.
In the manufacturing method of the MIS transistor of the fifth aspect of the present invention, suppression of the production of an interface state by the buffer layer in the sidewall spacer prevents deterioration in transistor characteristics.
In the manufacturing method of the MIS transistor of the sixth aspect of the present invention, the MIS transistor has improved in hot carrier resistance.
The object of the present invention is to prevent deterioration in gate resistance, decrease in reliability of a gate oxide film, and electrical short between a gate and source/drain electrodes by controlling lateral growth of the cobalt silicide film under the sidewall spacer.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.